1. Field of the Invention
This invention relates to an electronic system and, more particularly, to a circuit, apparatus and method which can shift a signal within a pair of signals clocked at the same frequency to achieve a ninety degree phase differential between transitions of the signal pair.
2. Description of the Related Art
Demands of modern day processing requires attention be paid to high speed data transmission. Many conventional microprocessors operate at clock speeds in excess of several hundred MHz. Communication across a network or microprocessors can exceed transmission rates of, e.g., 1.0 gigabit per second. Proposed ethernet and fibre channel standards mandate an encoded baud rate in the 1.25 Gb/s range.
To achieve high speed data rates, a clocking signal must be derived to which the data is synchronized. A well designed phase-locked loop ("PLL") can lock to high speed data rates provided fluctuations or "jitter" of data across the transmission media is not excessive. A PLL can therefore recover high speed clocks if properly designed. A crystal oscillator dedicated to the receiving device, and therefore placed outside the transmission media, demonstrates less jitter problems but is not always capable of achieving the higher clocking frequencies.
A clocking multiplier may be used in addition to the PLL and/or crystal oscillator to achieve a stable clocking signal. In a simple form, a clocking multiplier can be realized as a logic gate to which properly defined signals are presented. If the signals are of equal frequency, and transitions of one signal are delayed relative to the other signal, the clocking multiplier can produce an output approximately twice the frequency of the input signals. More importantly, if the phase of one of the clocking input signals is separated by one quarter cycle, or 90 degrees, the clocking multiplier can produce an output signal having a 50% duty cycle at twice the clocking input signal frequency.
It therefore appears advantageous to derive a pair of signals of equal frequency having a 90.degree. phase shift, or skew, from each other. If the signals are thusly formed, not only can a clocking multiplier be achieved, but also other applications can be derived. The clocking multiplier can be used in conjunction with either a crystal oscillator or a PLL output to further enhance the clocking rate at which, for example, the receiving device operates. A clocking multiplier which produces an output signal having a 50% duty cycle is beneficial in high speed environments where the receiving device must sync to rising and falling edges of the clock signal with very little time margin therebetween.
It would be desirous to derive a circuit which can reliably and accurately produce a pair of signals which transition at the same frequency but at a 90.degree. phase difference. The signal pair can be used in multiple applications, and certainly is not limited to that of a clock multiplier. Whatever the application, a circuit which can produce such signals must do so over a broad frequency range and phase differences encountered by clock signals being manipulated to achieve the desired phase difference.